Skip to content

Issues: llvm/circt

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

700 Open 1,436 Closed
700 Open 1,436 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[Seq] Counters
#8002 opened Dec 17, 2024 by teqdruid
@seldridge @darthscsi
1
CIRCT Regression tests Failed in nixpkgs
#8000 opened Dec 17, 2024 by unlsycn
[FIRRTL] IMDCE: not removing all dead instances FIRRTL Involving the `firrtl` dialect
#7992 opened Dec 13, 2024 by youngar
[FIRRTL] better wire canonicalization FIRRTL Involving the `firrtl` dialect
#7990 opened Dec 13, 2024 by youngar
[LLHD] Improve llhd-desequentialize pass
#7989 opened Dec 13, 2024 by AndreyVV-100
[InstanceChoice][FIRRTL] Ensure instance graph can handle InstanceChoiceOp
#7987 opened Dec 13, 2024 by prithayan
@prithayan
Build and test LLVM/MLIR Failed
#7984 opened Dec 13, 2024 by quanchenliu
1
[HWArith] Lowering to HW with type aliases HWArith The `hwarith` dialect
#7961 opened Dec 9, 2024 by teqdruid
1
[DCToHW] Pass creates invalid ESI connections DC
#7949 opened Dec 4, 2024 by teqdruid
5
[Arc] Introduce a Python simulation script generator for arcilator
#7942 opened Dec 4, 2024 by gtxzsxxk
3
[ESI] Attribute documentation not rendered correctly documentation Improvements or additions to documentation ESI
#7938 opened Dec 3, 2024 by maerhart
@teqdruid
[AIG] Pass documentation rendered incorrectly documentation Improvements or additions to documentation
#7937 opened Dec 3, 2024 by maerhart
@uenoku
[Verilog][FIRRTL] Improve $signed Elision FIRRTL Involving the `firrtl` dialect Verilog Quality
#7935 opened Dec 2, 2024 by seldridge
[MooreToCore] LSB and MSB support in moore dialect
#7925 opened Nov 29, 2024 by AndreyVV-100
[MooreToCore] moore.extract is converted to hw.array_slice when array's element type is also array
#7918 opened Nov 28, 2024 by slowlime
[FIRRTL] LowerLayers RefSend could be Canonicalized Away FIRRTL Involving the `firrtl` dialect
#7896 opened Nov 26, 2024 by seldridge
[FIRRTL] Can not canonicalize away memories without more care bug Something isn't working FIRRTL Involving the `firrtl` dialect
#7880 opened Nov 22, 2024 by youngar
[HandshakeToDC] Tech debt: clk/rst inserted later than they probably should be HandshakeToDC
#7851 opened Nov 19, 2024 by teqdruid
[HandshakeToHW] Asserts with core dialects operations HandshakeToHW
#7850 opened Nov 19, 2024 by teqdruid
[FIRRTL] smem with read address from port does not work
#7834 opened Nov 19, 2024 by jackkoenig
1
[HandshakeToDC] Missing lowering for InstanceOp HandshakeToDC
#7828 opened Nov 15, 2024 by teqdruid
@mortbopet
[HandshakeToDC] Missing cf conversions and memory stuff HandshakeToDC
#7826 opened Nov 15, 2024 by teqdruid
@mortbopet
3
[ImportVerilog] How to implement SVA in Moore? ImportVerilog
#7801 opened Nov 12, 2024 by chenbo-again
1
[FIRRTL] Remove backwards compatibility flag in Dedup FIRRTL Involving the `firrtl` dialect
#7800 opened Nov 12, 2024 by mikeurbach
[comb] Missing ~(~foo) canonicalization when foo is defined in another region
#7797 opened Nov 12, 2024 by rwy7
1
ProTip! Add no:assignee to see everything that’s not assigned.