Permute the pass pipeline to coalesce before setting up the matmul

[alexbaden]

Required for #2834

Two reasons to do this - one, it properly tags the layouts with their memory order very early in the TTGIR pipeline. And two, it moves our TTGIR pipeline closer to upstream. I am splitting the change to isolate any regressions or undesired behavior caused by this change vs changing the DPAS layouts in #2834.

cc #2354

[alexbaden]

Benchmark run: https://benchmarks.glados.intel.com/d/1pXX4hUSz/microbenchmarks?orgId=1&var-tag=ci%7Cci-adv%7Cci-dflt%7Cmovecoalesce&var-bench=All&var-device=Intel%28R%29%20Data%20Center%20GPU%20Max%201550&var-compiler=triton&var-compiler=xetla&var-compiler=onednn&var-backend=All&var-baseline_backend=xetla-ci-XPU%201550&var-target_backend=triton-ci-XPU%201550

Results appear to be in line with main, all deviations in the plots are within a min/max run from the last few days. This is ready for review.

[etiotto]

I wonder whether FlashAttention (using the default codegen path + dev IGC) is ok. @alexbaden ?

[alexbaden]

Is that covered by the attn plot in the microbenchmarks link I posted above?

[whitneywhtsang]

Is that covered by the attn plot in the microbenchmarks link I posted above?

No, need to run with igc-18251 runner.

[alexbaden]

Flash attention looks ok (as do the rest of the devigc benchmarks): https://benchmarks.glados.intel.com/d/1pXX4hUSz/microbenchmarks?orgId=1&var-tag=ci%7Cci-adv%7Cci-dflt%7Cmovecoalesce%7Cmovecoalescedevigc%7Cigc-18251&var-bench=All&var-device=Intel%28R%29%20Data%20Center%20GPU%20Max%201550&var-compiler=triton&var-compiler=xetla&var-compiler=onednn&var-backend=All&var-baseline_backend=xetla-ci-XPU%201550&var-target_backend=triton-ci-XPU%201550