Add support for Cortex-M7 r0p1 CPUs #5
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Cortex-M7 CPUs have that bit set by default and cannot be written. Signed-off-by: Jean Pierre Dudey <[email protected]>
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Added 4edadba as the demonstrator for drone-os/drone-core#16 |
The STREX instruction doesn't permits the Rd register to be the same as Rt and Rn, this applies to Cortex-M7 as well to Cortex-M4, and probably others too. Signed-off-by: Jean Pierre Dudey <[email protected]>
Signed-off-by: Jean Pierre Dudey <[email protected]>
These fields are available only for Cortex-M targets with an instruction and data cache. As of now only Cortex-M7 and Cortex-M35P have options for these caches. Signed-off-by: Jean Pierre Dudey <[email protected]>
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Almost no changes to the code, only the specific bits for Cortex-M7. Also, should the register definition for SCB.CCR.STKALIGN be changed? On Cortex-M7 it's read-only unlike for other Cortex-M processors, I tried feature gating only the field but it didn't work, so I had to do the entire register block, so I only removed the line of code that sets that specific bit (for Cortex-M7 is already set).