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CD.qsf.bak
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CD.qsf.bak
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 15:49:23 April 26, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CD_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY REGANEL
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:49:23 APRIL 26, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name BDF_FILE EXP5decode.bdf
set_global_assignment -name BDF_FILE Blocoplaca.bdf
set_global_assignment -name BDF_FILE BlockDuplu4x1.bdf
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name BDF_FILE multiplexdecox.bdf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform2.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform3.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform4.vwf
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name BDF_FILE SomadorCompleto.bdf
set_global_assignment -name BSF_FILE SomadorCompleto.bsf
set_global_assignment -name BDF_FILE MUX2POR1.bdf
set_global_assignment -name BSF_FILE MUX2POR1.bsf
set_global_assignment -name BDF_FILE SomadorSubtrator.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name BDF_FILE Multiplicador.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name BDF_FILE BCDCIMA.bdf
set_global_assignment -name BDF_FILE BCDBAIXO.bdf
set_global_assignment -name BDF_FILE MUX8ENTR.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform0.vwf
set_global_assignment -name BDF_FILE TransformarNeg.bdf
set_global_assignment -name BDF_FILE ULA.bdf
set_global_assignment -name BDF_FILE 7SEG.bdf
set_global_assignment -name BDF_FILE 7segsinal.bdf
set_global_assignment -name BDF_FILE TrabalhoFinal.bdf
set_global_assignment -name BDF_FILE FFD.bdf
set_global_assignment -name BDF_FILE REGANEL.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "D:/altera/13.0sp1/Waveform1.vwf"