STM32G4 dual flash bank configuration

[u6bkep]

I was having some trouble with the flash erase routines in the STM32g4 HAL, so I did some digging. The first issue I cam across was missing register definitions, so I fixed those. pull request incoming. Then I noticed the G4, category 3 devices at least, default to dual bank mode meaning any attempt to erase any data in the second half of ROM will fail because the page offset is calculated incorrectly. I have confirmed erasing a page in bank 2 can be done by running the erase sequence with manual register writes.

now I need some advice on how to move forward with this chip. Is there a recommended way in the HAL to configure single bank mode so the erase function works? or is the correct solution to modify the the metadata to reflect the two memory banks?

[Dirbaio]

The metadata and the embassy-stm32 implementation are for single-bank mode.

The problem is the firmware itself can't switch the chip from dual to single bank mode since it shuffles the flash, corrupting the firmware. You have to set it beforehand before flashing. I think ST's tools can do it, maybe probe-rs can also do it by writing the right value by flashing to that option byte address.

I think the only "fix" we can do in embassy-stm32 is to detect the chip is in dual-bank mode and panic, with a message for the user.

Dual-bank G4s are a bit cursed because there's a hole between the banks (unless you have the biggest flash size, 512kb). So you can't pretend they're a single bigger contiguous flash region. Erase size also changes: 2kb in dual bank, 4kb in single bank. So i'd recommend sticking to single bank if you can.