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In order to estimate the impact of Apple Silicon-based cloud services such as EC2 Mac instances and Scaleway Apple Silicon, we need a model for Apple M chips.
This means assessing the impact of the following components, all built into the same system-on-a-chip (SoC):
CPU (heterogeneous ARM big.LITTLE architecture, essentially two groups of cores with different specs)
Memory (LPDDR4X for M1, LPDDR5 for M2, shared by all components of the SoC)
I have created a PR to add the specs for the M1 and M2 ranges in the existing CPU format here: #349. However, I fear that this will not give particularly accurate results, as the SoC doesn't really fit with the existing component-based model (with separate CPU, memory, GPU etc.).
Here are a few open questions:
Is the 5nm process used for Apple Silicon significantly more (or less) resource intensive than the base process that we assume in the existing CPU impact factors (which is 12nm IIRC)? Is it still valid to use the existing CPU impact values?
Can we ignore non-CPU component-specific calculations when dealing with SoCs given that the components are embedded in the SoC itself? For example, for an Apple Silicon server, can I just say ram.capacity=0, and assume the impact of the memory is implicitly captured in the impact of the SoC?
Do we count all the cores (CPU, GPU and Neural Engine) as the total core count for the processor, or just the CPU cores? If not, are we effectively ignoring the GPU and Neural Engine parts?
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Context
In order to estimate the impact of Apple Silicon-based cloud services such as EC2 Mac instances and Scaleway Apple Silicon, we need a model for Apple M chips.
This means assessing the impact of the following components, all built into the same system-on-a-chip (SoC):
Useful links:
Discussion
I have created a PR to add the specs for the M1 and M2 ranges in the existing CPU format here: #349. However, I fear that this will not give particularly accurate results, as the SoC doesn't really fit with the existing component-based model (with separate CPU, memory, GPU etc.).
Here are a few open questions:
ram.capacity=0
, and assume the impact of the memory is implicitly captured in the impact of the SoC?Beta Was this translation helpful? Give feedback.
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